1. Field of the Invention
This invention relates to an improved phase-locked-loop (PLL) circuit for use in a frequency synthesizer or the like, and particularly to a PLL circuit in which the charge pump drive current is varied depending on the operating mode.
2. Description of the Prior Art
FIG. 1 shows the arrangement of a conventional 2-mode PLL circuit. In FIG. 1, reference number 1 denotes a reference oscillator having its output fed to a frequency divider 2, whose output is applied as a reference input to a phase comparator 3. The phase comparator 3 has a phase-lead output and a phase-lag output both supplied to a charge pump 4, and further has a phase lock signal 10 used as a control signal for a switch 5. The output of the charge pump 4 is fed to a low-pass filter 7, which has its characteristics changed by means of the switch 5. The low-pass filter 7 feeds its output to a voltage-controlled oscillator (VCO) 6, whose output is sent out as the output 9 of the PLL circuit and at the same time fed to a frequency divider 8. The output of the frequency divider 8 is applied to the other input of the phase comparator 3.
The operation of the above-described conventional PLL circuit is as follows. The circuit arrangement of FIG. 1, except for the presence of the switch 5, is a commonly used phase lock loop circuit which operates for an oscillation frequency f.sub.R of the reference oscillator 1, a division ratio M of the frequency divider 2 and a division ratio N of the frequency divider 8 to produce an output 9 at a frequency fo given as follows. ##EQU1##
The output frequency fo can be variable through the provision of frequency dividers 2 and 8 having variable frequency division ratios M and N. The characteristics of the loop are expressed in terms of the loop gain and the transfer characteristics of the low-pass filter 7, and when an RC filter shown in FIG. 1 is used as the low-pass filter 7, this loop becomes a second-order loop.
For a supply voltage Vp of the charge pump and a modulation sensitivity Kv of the VCO, the natural frequency (.omega.n) and damping factor (.zeta.) which determine the PLL response are given as follows. ##EQU2## Accordingly, by closing the switch 5 to short the resistor r.sub.2, the value of .omega.n increases, the natural frequency of PLL rises, and the system has a faster response. Therefore, when the PLL is in a non-locked mode, it can be pulled into synchronization much faster by appling the phase lock signal 10 to close the switch 5. In a locked mode, the switch 5 is made open with a result of a smaller .omega.n, and the circuit is advantageous in noise suppression and stability. Accordingly, by switching the filter characteristics, the PLL circuit can have consistent characteristics of fast response and high noise immunity.
However, the above conventional 2-mode PLL circuit employs a switch for changing the filter transfer characteristics depending on the operating mode, and it must be an external switch when the circuit is fabricated as an integrated circuit module, which hampers the circuit miniaturization. In addition, the mode switch is apt to disturb the operation of the voltage-controlled oscillator.